FPGA design approach outperforms ASICs

Once used only for gluing logic, FPGAs have evolved where system-on-chip (SoC) designs can be built on a single device. The number of gates and functions has increased dramatically to compete with the functionality traditionally available only through ASIC devices. This paper describes some advantages of the FPGA design approach over ASICs, including early time-to-market, easy transition to structured ASICs, and reduced NRE costs.

As FPGA devices advance in resources and performance, the latest FPGAs have begun to offer "platform" solutions that can be easily customized for system connectivity, DSP, and data processing applications. As platform solutions become increasingly important, leading FPGA vendors are coming up with easy-to-use design development tools.

These platform-building tools accelerate time-to-market by automating the system definition and integration phases of programmable-on-chip (SOPC) development systems. These tools not only improve design efficiency but also reduce the cost of purchasing these tools from third-party EDA vendors. Using these tools, system designers can define a complete system, from hardware to software, within a single device and in a fraction of the time of a traditional system-on-chip (SOC) design.

DSP Design

DSP system design in programmable logic devices requires high-level algorithms and hardware description language (HDL) development tools. Major FPGA vendors offer DSP build tools that combine the algorithm development, simulation, and verification capabilities of Matlab and Simulink with synthesis, simulation, and layout routing.

These tools help designers create hardware representations of DSP designs in an algorithm-friendly development environment, thereby shortening the DSP design cycle. Existing Matlab functionality and Simulink modules can be combined with FPGA vendor modules and vendor intellectual property (IP) functionality to link system-level design and implementation with DSP algorithm development. This allows the system, algorithm, and hardware designers to share a common development platform.

Designers can create hardware implementations of systems modeled in Simulink in sample time. DSP tools include bit- and cycle-accurate Simulink modules covering basic operations such as arithmetic or memory functions. With the availability of such tools, designers can generate and optimize algorithm designs in a fraction of the time it would take to write RTL manually.

IP Integration

With the advent of millions of FPGAs, designers must leverage as much IP as possible to improve efficiency. Third-party IP integration is not easy to perform, as one must verify the IP to the target technology and then ensure that the IP meets regional and performance specifications.

But with FPGAs, vendors themselves can have trouble verifying the region and performance of third-party and internally developed IP. The biggest advantage of a platform-based design is that it supports the integration of proprietary logic with third-party IP.

The challenge with any system-on-a-chip FPGA is to verify the entire system's functionality, including the processor core, third-party IP, and proprietary logic. To perform such verification and high-speed simulators, verification engineers also need a suite of verification tools. The FPGA design methodology supports formal verification and static timing analysis to support system verification.

Tool Support

The FPGA design flow supports using third-party EDA tools to perform design flow tasks such as static timing analysis, formal verification and RTL, and gate-level simulation.

Traditionally, FPGA design and PCB design have been done separately by different design teams using multiple EDA tools and flows. This can create board-level connectivity and timing convergence challenges, impacting designers' performance and time-to-market. The new EDA tools combine PCB solutions and FPGA vendor design tools with helping enable smooth integration of FPGAs on FPGAs.

Transitioning to Structured ASICs

As the demand for FPGA parts increases, FPGA suppliers offer a comprehensive ASIC alternative called Structured ASICs provides a complete solution from prototype to high-volume production. It maintains its FPGA's robust functionality and high-performance architecture, with programmability eliminated. Structured ASIC solutions not only improve performance but also significantly reduce cost.

As new technologies emerge in the FPGA space, design companies can choose options other than ASICs. With mask costs approaching the $1 million price tag and NRE costs approaching another million dollars, it is difficult to justify a smaller unit size for ASICs. On the other hand, FPGAs improve the ability to build systems on a chip with over a million ASIC equivalent gates and several megabits of on-chip RAM. for high volume production, structured ASIC solutions combine the cost advantages of ASICs with the low-risk solutions of FPGAs.