Challenges of SoC and Heterogeneous Computing

In the complex heterogeneous computing ecosystem, developing on-chip network interconnects is critical to advancing system-on-chip technology.

The computing ecosystem has fully embraced the concept of heterogeneous computing - and the result has been a proliferation of systems-on-chip (SoC). SoC can now be found in virtually every high-performance computing platform on the market.

The Network on Chip (NoC) is a less frequently discussed but equally important technology. As SoC continue to evolve, the development of NoCs will only continue to grow. Recently, UK-based Sondrel highlighted the importance of NoC by announcing that it is using Arteris' FlexNoC IP as the NoC backbone for Sondrel SoC. Sondrel explains that designers often overlook the importance of this data flow aspect because the network-on-chip (NoC) design is complex, and difficult to verify that performance requirements are met in all cases, as there are many extreme cases. This leads to sub-optimal data transfer and SoC delivery of the NoC.

SoC and the challenges of heterogeneous computing

SoC is a single-chip solution consisting of several different compute and functional blocks in the same chip. soC contains heterogeneous compute and hardware acceleration, where there are dedicated compute blocks for specific compute-intensive workloads. For this reason, we typically see an SoC consisting of a few more general-purpose compute blocks, such as CPUs and GPUs, and many gas pedal blocks, such as neural processing units (NPUs) and digital signal processors (DSPs).

SoC software typically abstracts functionality to be easily programmed and connected. The advantage of SoCs is that they are cheaper, smaller, and more energy efficient. The disadvantage is that, unlike full-size computers, they are locked into their configuration.

While the solution brings higher performance and efficiency, it has several control and management issues. In data-intensive applications, SoCs face the challenge of controlling, organizing, and managing the large amounts of data they are expected to handle. Controlling the flow of data in and out of memory and the number of different functional blocks is a non-trivial issue from a layout planning perspective and a system perspective.

What is NoC?

To solve these data-related problems, almost every SoC relies on NoCs.

NoC interconnects almost every part of the SoC, creating a transparent and well-defined path for data to flow from one block to another. Typically, the NoC will consist of multiple segments of cabling and routers arranged to reduce parasitic effects and thus avoid greater losses and delays throughout the SoC. This usually forms a grid structure similar to an urban layout.

The NoC controls the flow of data throughout the SoC through the use of network interface (NI) modules. These modules are typically used to convert packets generated by the processor core into fixed-length flow control numbers. These numbers allow routers within the NoC to direct the data appropriately to the desired functional blocks.

Traditionally, NoC functionality can be defined as one of several layers, including the application layer, transport layer, network layer, data link layer, and physical layer. For this reason, an NoC router will require hardware and software implementations to support the functionality of a given layer.

Typically, designers start their chip design with a floor plan or NoC. The new approach stabilizes the performance requirements by performing performance exploration at a very early stage to stabilize and test the architecture to reduce the possibility of changes, thus stabilizing the floor plan and NoC thus avoiding some surprises. Performance exploration solves the problem that IP blocks are usually verified in isolation. However, this does not consider their interaction with other IP blocks. The more IPs on the chip, the higher the chance they could seriously impact chip performance.

Sondrel uses FlexNoC

On June 22, 2022, Sondrel revealed that it uses Arteris' FlexNoC IP as the NoC backbone for all its SoC solutions.

Arteris explains that NoC interconnects make up the SoC architecture.

Sondrel sees some specific benefits of using FlexNoC interconnect technology, starting with the ability to reduce area and line count.

This is accomplished by leveraging transport layer packing and serialization capabilities so that NoC architects can control exactly which parts of the NoC can benefit from the reduced lines and area without compromising performance requirements. Secondly, power consumption is reduced by using power management features such as the option to configure clock domain crossover and clock gating support to ensure power consumption is within the power budget. An additional benefit is the ability to create physically aware designs. The design team can hand off the netlist to the back-end team to ensure timing requirements are met. The NoC design methodology considers SoC layout planning and any physical design constraints on that design from the outset.

Finally, FlexNoc has advanced configuration tools and an excellent UI. the suite of tools provided to generate high-performance, timing-clean interconnects is intuitive and easy for NoC architects to become familiar with, resulting in increased productivity.

Like Sondrel, many companies in the industry compete to produce the best NoC IP to produce SoCs with lower area and power consumption while making SoC designs easier to implement.