STM32MP153CAD3T STMicroelectronics MPU

STM32MP153CAD3T Overview

The STM32MP153C/F devices are based on the high-performance dual-core Arm® Cortex®-A7 32-bit RISC core operating at up to 800 MHz. The Cortex-A7 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU and a 256-Kbyte level2 cache. The Cortex-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20% more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9.

The Cortex-A7 incorporates all features of the high-performance Cortex-A15 and Cortex-A17 processors, including virtualization support in hardware, NEON?, and 128-bit AMBA®4 AXI bus interface.
The STM32MP153C/F devices also embed a Cortex® -M4 32-bit RISC core operating at up to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision which supports Arm® single-precision data-processing instructions and data types. The Cortex® -M4 supports a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
The STM32MP153C/F devices provide an external SDRAM interface supporting external memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L up to 533 MHz.
The STM32MP153C/F devices incorporate high-speed embedded memories with 708 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix and a 64-bit multi layer AXI interconnect supporting internal and external memories access.
All the devices offer two ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell. The devices support six digital filters for external sigma delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

Features

32-bit dual-core Arm Cortex-A7
- L1 32-Kbyte I / 32-Kbyte D for each core
- 256-Kbyte unified level 2 cache
- Arm NEON and Arm TrustZone
32-bit Arm Cortex-M4 with FPU/MPU
- Up to 209 MHz (Up to 703 CoreMark)

Memories

External DDR memory up to 1 Gbyte
- up to LPDDR2/LPDDR3-1066 16/32-bit
- up to DDR3/DDR3L-1066 16/32-bit
708 Kbytes of internal SRAM: 256 Kbytes of AXI SYSRAM + 384 Kbytes of AHB SRAM + 64 Kbytes of AHB SRAM in Backup domain and 4 Kbytes of SRAM in Backup domain
Dual mode Quad-SPI memory interface
Flexible external memory controller with up to 16-bit data bus: parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC

Security/safety

Secure boot, TrustZone peripherals, active tamper
Cortex-M4 resources isolation

Reset and power management

1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
POR, PDR, PVD and BOR
On-chip LDOs (RETRAM, BKPSRAM, USB 1.8 V, 1.1 V)
Backup regulator (~0.9 V)
Internal temperature sensors
Low-power modes: Sleep, Stop and Standby
DDR memory retention in Standby mode
Controls for PMIC companion chip

Low-power consumption

Total current consumption down to 2 μA (Standby mode, no RTC, no LSE, no BKPSRAM, no RETRAM)

Clock management

Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator
External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
5 × PLLs with fractional mode

General-purpose input/outputs

Up to 176 I/O ports with interrupt capability
- Up to 8 secure I/Os
- Up to 6 Wakeup, 3 tampers, 1 active tamper

Interconnect matrix

2 bus matrices
- 64-bit Arm AMBA AXI interconnect, up to 266 MHz
- 32-bit Arm AMBA AHB interconnect, up to 209 MHz

3 DMA controllers to unload the CPU

48 physical channels in total
1 × high-speed general-purpose master direct memory access controller (MDMA)
2 × dual-port DMAs with FIFO and request router capabilities for optimal peripheral management