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Home > Embedded ICs > 32bit MCU > SPC58NG84E7QEH0Y
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SPC58NG84E7QEH0Y

SPC58NG84E7QEH0Y

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Features

  • 32-bit Power Architecture technology CPU
  • Core frequency as high as 180 MHz
  • Variable Length Encoding (VLE)
  • Floating Point, End-to-End Error Correction
  • 6582 KB (6144 KB code flash+ 256 KB data flash) on-chip flash memory:
    • supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
    • Supports read while read between the two code Flash partitions.
  • 608 KB on-chip general-purpose SRAM (in addition to 160 KB core local data RAM): 64KB in CPU_0, 64 KB in CPU_1 and 32 KB in CPU_2
  • 182 KB HSM dedicated flash memory (144 KB code + 32 KB data)
  • Multi-channel direct memory access controller (eDMA)
    • one eDMA with 64 channels
    • one eDMA with 32 channels
  • 1 interrupt controller (INTC)
  • Comprehensive new generation ASIL-D safety concept:
    • ASIL-D of ISO 26262
    • One CPU channel in lockstep
    • Logic BIST
    • FCCU for collection and reaction to failure notifications
    • Memory BIST
    • Cyclic redundancy check (CRC) unit
    • Memory Error Management Unit (MEMU) for collection and reporting of error events in memories
  • Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC

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