PIC18F6620 MICROCHIP Controller

PIC18F6620 Overview

DEVICE OVERVIEW
This document contains device specific information for
the following devices:

High-Performance RISC CPU:
• C compiler optimized architecture/instruction set:
   - Source code compatible with the PIC16 and PIC17 instruction sets
• Linear program memory addressing to 128 Kbytes
• Linear data memory addressing to 3840 bytes
• 1 Kbyte of data EEPROM
• Up to 10 MIPs operation:
   - DC – 40 MHz osc./clock input
   - 4 MHz – 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 31-level, software accessible hardware stack
• 8 x 8 Single Cycle Hardware Multiplier

CMOS Technology:
• Low-power, high-speed Flash technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges

Features

Special Microcontroller :
• 100,000 erase/write cycle Enhanced Flash program memory typical
• 1,000,000 erase/write cycle Data EEPROM memory typical
• 1 second programming time
• Flash/Data EEPROM Retention: > 40 years
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming™ (ICSP™) via two pins
• MPLAB® In-Circuit Debug (ICD) via two pins

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