P3041NSN7PNC NXP MPU

P3041NSN7PNC Overview

The QorIQ® P3041 processor is an optimized quad-core device that leverages architectural features pioneered in the P4 platform. Built on Power Architecture® technology, the P3041 fits into many of the same applications as the P4 platform processors, yet is designed to offer a more power- and cost-efficient solution.

The P3041 includes P4 platform features such as the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet® switch fabric which eliminates internal bottlenecks. This enables architectural compatibility from the P3041 to the P4 platform and also to the P5 platform, which uses the same architecture. P3041 is pin-compatible with P4040, P4080, P5010, and P5020.

Features

Four high-performance e500mc cores up to 1.5 GHz
Three level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 1 MB shared CorNet platform cache

Networking Elements

One 10 Gbps Ethernet (XAUI) controllers
Five 1 Gbps Ethernet controllers available on SGMII, 2.5 Gbps SGMII, or RGMII

Accelerators and Memory Control

64-bit (72-bit with ECC) DDR2/3 memory controller up to 1.3 GHz data rate
DPAA incorporating acceleration for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion management
- Hardware buffer management for buffer allocation and de-allocation
- Encryption (SEC 4.2)
- RegEx Pattern Matching (PME 2.1)

Basic Peripherals and Interconnect

High-speed peripheral interfaces:
- Four PCI Express® v2.0 controllers/ports running at up to 5 GHz
- Two Serial RapidIO® 1.3/2.1 controllers/ports running at up to 5 GHz, with Type 9 and 11 messaging
- Two SATA 2.0 interfaces
- Two USB 2.0 controllers with integrated PHY, enhanced local bus controller (eLBC), SD/MMC, serial peripheral interface (SPI) controller, four I²C controllers, two dual

Additional Features

Hardware hypervisor for safe partitioning of operating systems between cores
Trusted boot capability to ensure only the correct code is booted and that code is not reverse-engineered
Pin-and software-compatible with P4040, P4080, P5010, and P5020