MPC8543EVUAQG NXP MPU

MPC8543EVUAQG Overview

NXP has developed four next-generation PowerQUICC™ III processors based on the scalable e500 system-on-chip (SoC) platform and Power Architecture processor core. These PowerQUICC® III processors, the MPC8548E, MPC8547E, MPC8545E and MP8543E, are designed to deliver gigahertz-plus communications processing performance and advanced features with the exceptional integration and high-speed connectivity required by enterprise networking, telecom transmission and switching, 3G wireless infrastructure, storage and high-end imaging markets.. The processors are designed to offer clock speeds scaling up to 1.5 GHz. They combine the powerful processor core, enhanced peripherals and high-speed interconnect technology to balance processor performance with I/O system throughput.

The next-generation PowerQUICC III processors are based on NXP®.s 90 nanometer (nm) silicon-on-insulator (SOI) copper interconnect process technology, which enables processors to deliver higher performance with lower power dissipation. At 1.5 GHz, these new processors deliver a significant performance increase over current 130 nm PowerQUICC III devices.

The MPC8548E, MPC8547E, MPC8545E and MP8543/E processors offer a wide range of high-speed connectivity options, including Gigabit Ethernet, Serial RapidIO® technology and PCI Express. Support for these high-speed interfaces enables scalable connectivity to network processors and/or ASICs in the data plane while the PowerQUICC III handles complex, computationally demanding control plane processing tasks. These processors also feature next-generation double data rate (DDRII) memory controller, enhanced, Gigabit Ethernet support, double precision floating point and integrated security engines that support the Kasumi alogrithm needed for 3G wireless security. In addition, support is provided for XOR acceleration needed for parity in storage applications.

Features

Secure Communications Architecture leveraging Mocana's Device Security Framework technology
Embedded e500 core, scaling up to 1.5 GHz
- Dual Dispatch super-scaler, 7-stage pipeline design with out-of-order issue and execution
- 3065 MIPS at 1333 MHz (estimated Dhrystone 2.1)
Integrated L1/L2 cache
- L1 cache -32 KB data and 32 KB instruction cache with line-locking support
- L2 cache -512 KB (8-way set associative); 512 KB/256 KB/128 KB/64 KB can be used as SRAM
- L1 and L2 hardware coherency
- L2 configurable as SRAM, cache or stash cache
Integrated DDR memory controller with full ECC support, supporting:
- 200 MHz clock rate (400 MHz data rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM
- 266 MHz clock rate (up to 533 MHz data rate) DDR2 SDRAM
Double-precision embedded scalar and vector floating-point APUs
Memory management unit (MMU)
Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms.
Multiple PCI interface support
- 64-bit PCI 2.2 bus controller (up to 66 MHz, 3.3V I/O)
- 64-bit PCI-X bus controller (up to 133 MHz, 3.3V I/O), or
- Flexibility to configure two 32-bit PCI controllers
Four on-chip triple-speed Ethernet controllers (GMACs) supporting 10- and 100-Mbps, and 1-Gbps Ethernet/802.3 networks with MII, RMII, GMII, RGMII, RTBI and TBI physical interfaces.
- TCP/IP checksum acceleration
- Advanced QoS features
General-purpose I/O
Serial RapidIO and PCI Express high-speed interconnect interfaces, supporting
- Single x8 PCI Express, or
- Single x4 PCI Express and single 4x Serial RapidIO
On-chip network (OCeaN) switch fabric
Integrated four-channel DMA controller
Dual I2C interfaces and Dual Universal Asynchronous Receiver/Transmitter (DUART) support
Programmable interrupt controller (PIC)
General-purpose parallel I/O (GPIO)
IEEE 1149.1 JTAG test access port
1.1V core voltage with 3.3V and 2.5V I/O
783-pin FC-BGA package
This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch