MPC8260ACZUMHBB NXP MPU

MPC8260ACZUMHBB Overview

The MPC8260 PowerQUICC® II™ is an advanced integrated communications processor designed for the telecommunications and networking markets.

The MPC8260 now offers floating point support.

The MPC8260 PowerQUICC II can best be described as the next generation MPC860 PowerQUICC®, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.

Like the MPC860, the MPC8260 integrates two main components, the embedded G2 core and the Communications Processor Module (CPM). This dual-processor architecture consumes less power than traditional architectures because the CPM offloads peripheral tasks from the embedded G2 core. The CPM simultaneously supports three fast serial communications controllers (FCCs), two multichannel controllers (MCCs), four serial communications controllers (SCCs), two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I2C interface. The combination of the G2 core and the CPM, along with the versatility and performance of the MPC8260, provides customers with enormous potential in developing networking and communications products while significantly reducing time-to-market development stages.

Features

190 MIPS at 100 MHz (Dhrystone 2.1)
505 MIPS at 266 MHz (Dhrystone 2.1)
570 MIPS at 300 MHz (Dhrystone 2.1)
High-performance, superscalar microprocessor
Disable CPU mode
Supports the NXP® external L2 cache chip (MPC2605)
Improved low-power core
16 Kbyte data and 16 Kbyte instruction cache, four-way set associative
Memory Management Unit
Floating point unit enabled
Common on-chip processor (COP)

System Integration Unit (SIU)
- Memory Controller, including two dedicated SDRAM machines
- PCI up to 66 MHz (available in subsequent versions)
- Hardware bus monitor and software watchdog timer
- IEEE 1149.1 JTAG test access port
High-Performance Communications Processor Module (CPM) with operating frequency up to 133, 166, or 200 MHz
- G2 core and CPM may run at different frequencies
- Parallel I/0 Registers
- On-board 32 KBytes of dual-port RAM
- Two multi-channel controllers (MCCs) each supporting 128 full-duplex,64 Kbps, HDLC lines
- Virtual DMA Functionality
Three FCCs supporting:
- Up to 155 Mbps ATM SAR (maximum of two) (AAL0, AAL1, AAL2, AAL5)
- 10/100 Mbps Ethernet (up to three) (IEEE 802.3X with Flow Control)
- 45 Mbps HDLC/Transparent (up to three)
Two bus architectures: one 64-bit 60x bus and one 32-bit PCI or local bus
Two UTOPIA level-2 master/slave ports, both with multi-PHY support.
Three MII Interfaces
Eight TDM interfaces (T1/E1), two TDM ports can be glueless to T3/E3
1.8V or 2.0V internal and 3.3V I/O
300 MHz power consumption: 2.5 W
480 TBGA package (37.5 mm x 37.5 mm)