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NXP

MPC561MZP66

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MPC561MZP66 Overview

The MPC561 is a high-speed 32-bit control unit that combines high-performance data manipulation capabilities with powerful peripheral subsystems. This MCU is built up from standard modules that interface through a common intermodule bus (IMB).

Features

  • Precise exception model
  • Floating point
  • Extensive system development support
  • On-chip watchpoints and breakpoints
  • Background debug mode (BDM)
  • IEEE®ISTO 5001-1999 NEXUS class 3 debug interface
  • True 5-volt I/O
  • Two time processing units (TPU3) with 8 KB DPTRAM
  • 22-channel MIOS timer (MIOS14)
  • Two queued analog-to-digital converter modules (QADC64_A, QADC64_B) providing a total of 32 analog channels
  • Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)
  • One queued serial module with one queued SPI and two SCIs (QSMCM) 32 KB static RAM (CALRAM)

Applications

MPC5xx

Specifications

  • Core Processor PowerPC

  • Speed 66MHz

  • Operating Temperature -40℃ ~ 125℃ (TA)

  • Program Memory Type ROMless

  • RAM Size 32K x 8

  • Number of I/O 64

  • Peripherals POR, PWM, WDT

  • Mounting Type Surface Mount

  • Oscillator Type External

  • Supplier Device Package 388-PBGA (27x27)

  • Package / Case 388-BBGA

  • Core Size 32-Bit

  • Connectivity CANbus, EBI/EMI, SCI, SPI, UART/USART

  • Data Converters A/D 32x10b

  • Voltage - Supply (Vcc/Vdd) 2.5V ~ 2.7V

Circuit Diagram

MPC561

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