LPC43S30FET100E NXP 32bit MCU

LPC43S30FET100E Overview

The LPC43S30FET100 is a Arm Cortex-M4 based microcontroller for embeddedapplications which includes an Arm Cortex-M0 coprocessor, 264 kB of SRAM,security features with AES engine, advanced configurable peripherals such as the StateConfigurable Timer/PWM (SCTimer/PWM) and the Serial General-Purpose I/O (SGPIO)interface, two High-speed USB controllers, Ethernet,an external memory controller,and multiple digital and analog peripherals. The LPC43S30FET100 operates at CPUfrequencies of up to 204 MHz.

The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption,enhanced debug features, and a high level of support block integration. The Arm Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separatelocal instruction and data buses as well as a third bus for peripherals, and includes aninternal prefetch unit that supports speculative branching. The Arm Cortex-M4 supportssingle-cycle digital signal processing and SIMD instructions. A hardware floating-pointunit is integrated in the core.

The Arm Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which is code-and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor offers up to 204MHz performance with a simple instruction set and reduced code size. In LPC43Sx0, theCortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterativemultiplier.

Features

Cortex-M4 Processor core
- Arm Cortex-M4 processor, running at frequencies of up to 204 MHz.
- Built-in Memory Protection Unit (MPU) supporting eight regions.
- Built-in Nested Vectored Interrupt Controller (NVIC).
- Hardware floating-point unit making the core a Cortex-M4.
- Non-maskable Interrupt (NMI) input.
- JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watchpoints.
- Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
- System tick timer.
Cortex-M0 Processor core
- Arm Cortex-M0 coprocessor capable of off-loading the main Arm Cortex-M4Fapplication processor.
- Running at frequencies of up to 204 MHz.
- JTAG
- Built-in NVIC.
On-chip memory
- 264 kB SRAM for code and data use.
- Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually
- 64 kB ROM containing boot code and on-chip software drivers.
- 64 bit general-purpose OTP memory
- Two banks (256 bit total) One-Time Programmable (OTP) memory for AES keystorage One bank can store an encrypted key for decoding the boot image.
AES engine for encryption and decryption of the boot image and data with DMAsupport and programmable via a ROM-based API.
Clock generation unit
- Crystal oscillator with an operating range of 1 MHz to 25 MHz.
- 12 MHz Internal RC (IRC) oscillator trimmed to 1.5 % accuracy over temperatureand voltage.
- Ultra-low power Real-Time Clock (RTC) crystal oscillator.
- Three PLLs allow CPU operation up to the maximum CPU rate without the need fora high-frequency crystal. The second PLL is dedicated to the High-speed USB, thethird PLL can be used as audio PLL.
- Clock output.
Configurable digital peripherals
- Serial GPIO (SGPIO) interface.
- State Configurable Timer (SCTimer/PWM) subsystem on AHB.
- Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs andoutputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.
Serial interfaces
- Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to52 MB per second.
- 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for highthroughput at low CPU load. Support for IEEE 1588 time stamping/advanced timestamping (IEEE 1588-2008 v2).
- One High-speed USB 2.0 Host/Device/OTG interface with DMA support andon-chip high-speed PHY (USB0).
- One High-speed USB 2.0 Host/Device interface with DMA support, on-chipfull-speed PHY and ULPI interface to external high-speed PHY (USB1).
- USB interface electrical test software included in ROM USB stack.
- Four 550 UARTs with DMA support: one UART with full modem interface; oneUART with IrDA interface; three USARTs support UART synchronous mode and asmart card interface conforming to ISO7816 specification.
- Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controllerexcludes operation of all other peripherals connected to the same bus bridge
- Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMAsupport.
- One SPI controller.
- One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/Opins conforming to the full I²C-bus specification. Supports data rates of up to1 Mbit/s.
- One standard I²C-bus interface with monitor mode and with standard I/O pins.
- Two I²S interfaces, each with DMA support and with one input and one output.
Digital peripherals
- External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,and SDRAM devices.
- Secure Digital Input Output (SD/MMC) card interface.
- Eight-channel General-Purpose DMA controller can access all memories on theAHB and all DMA-capable AHB slaves.
- Up to 49 General-Purpose Input/Output (GPIO) pins with configurablepull-up/pull-down resistors.
- GPIO registers are located on the AHB for fast access. GPIO ports have DMAsupport.
- Up to eight GPIO pins can be selected from all GPIO pins as edge and levelsensitive interrupt sources.
- Two GPIO group interrupt modules enable an interrupt based on a programmablepattern of input states of a group of GPIO pins.
- Four general-purpose timer/counters with capture and match capabilities.
- Repetitive Interrupt timer (RI timer).
- Windowed watchdog timer (WWDT).
- Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytesof battery powered backup registers.
- Alarm timer; can be battery powered.
Analog peripherals
- One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
- Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.Up to eight input channels per ADC.
Unique ID for each device.
Power
- Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator forthe core supply and the RTC power domain.
- RTC power domain can be powered separately by a 3 V battery supply.
- Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deeppower-down.
- Processor wake-up from Sleep mode via wake-up interrupts from variousperipherals.
- Wake-up from Deep-sleep, Power-down, and Deep power-down modes viaexternal interrupts and interrupts generated by battery powered blocks in the RTCpower domain.
- Brownout detect with four separate thresholds for interrupt and forced reset.
- Power-On Reset (POR).
- Available as TFBGA100 package.

Target Applications

Communication hubs
Automotive aftermarket
Power management
Consumer health devices
Embedded audio applications
Industrial control
Industrial automation
White goods

Applications

LPC43xx

Specifications

Core Processor ARM Cortex M4/M0
Speed 204MHz
Operating Temperature -40℃ ~ 85℃ (TA)
Program Memory Type ROMless
RAM Size 264K x 8
Number of I/O 49
Peripherals Brown-out Detect/Reset, DMA, I2S, POR, WDT
Mounting Type Surface Mount
Oscillator Type Internal
Supplier Device Package 100-TFBGA (9x9)
Package / Case 100-TFBGA
Core Size 32-Bit Dual-Core
Connectivity CANbus, EBI/EMI, Ethernet, I2C, IrDA, Microwire, SD, SPI, SSI, SSP, UART/USART, USB, USB OTG
Data Converters A/D 4x10b; D/A 1x10b
Voltage - Supply (Vcc/Vdd) 2.2V ~ 3.6V