ATSAMD51G18A-MU Microchip 32bit MCU

ATSAMD51G18A-MU Overview

The SAM D51 highperformance micro-controller series features a 32-bit ARM® Cortex®-M4processor with Floating Point Unit (FPU), running up to 120 MHz ,up to 1 MBDual Panel Flash with ECC, and up to 256 KB of SRAM with ECC.

Series offers excellent features with class leading power performance ideal for multiple market segments.

Key features

· Quad Serial Peripheral Interface(QSPI) with Execute in Place (XIP) Support.

· Up to 2 Secure Digital Host Controller (SDHC)

· Inter-IC Sound(I2S)Controller for Audio

· Peripheral Touch Controller (PTC) supporting up to 256 channels of capacitive touch .

· Full speed USB with embedded Host/device.

· Supports 5 Low power modes with class leading 65µA/MHz Active Power Performance.

· Integrated security including Asymmetric and Symmetric Crypto hardware acceleration

· Serial communication (SERCOM) ports configurable as UART/USART, ISO 7816, SPI or I2C

Supported by MPLAB X IDE and MPLAB Harmony.

ECAD Model

Symbol

Footprint

Features

ARM Cortex-M4F CPU running at up to 120 MHz
Floating Point Unit (FPU)
Embedded Trace Module (ETM) with instruction trace stream
Error Correction Code (ECC)
Dual bank with Read-While-Write (RWW) support
EEPROM hardware emulation
Error Correction Code (ECC) RAM option
Up to 4 KB of Tightly Coupled Memory (TCM)
Up to 8 KB additional SRAM with backup retention capability
Five Low Power Modes (Idle, Standby, Hibernate, Backup, and Off )
Sleep Walking peripherals.
Battery backup support
Embedded Buck/LDO regulator supporting on-the-fly selection.
65µA/MHz active power consumption.
Five confidential modes of operation (ECB, CBC, CFB, OFB, CTR)
True Random Number Generator (TRNG)
RSA, DSA
Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA
32-channel Direct Memory Access Controller (DMAC)
Compatibility with SD and SDHC Memory Card Specification Version 3.01
Compatibility with SDIO Specification Version 3.0
Compliant with JDEC specification, MMC memory cards V4.51
eXecute-In-Place (XIP) support
Up to 75 MHz SDR operation and DDR support
Embedded host and device function
USART with full-duplex and single-wire half-duplex configuration
ISO7816
I2C up to 3.4MHz
SPI
LIN master/slave
RS485
SPI inter-byte space
Up to 14-bit parallel capture mode
Up to 256 channel capacitive touch and proximity sensing
32-channel Event System
16-bit ,32-bit or 8-bit TC with two compare/capture channels
Two 24-bit Timer/Counters for Control (TCC), with extended functions:
Up to 5 wake-up pins with tamper detection and de-bouncing filter
Watchdog Timer (WDT) with Window mode
CRC-32 generator
Position Decoder (PDEC)
Frequency meter (FREQM)
One Configurable Custom Logic (CCL)
Differential and single-ended input
Automatic offset and gain error compensation
Oversampling and decimation in hardware to support 13-, 14-, 15-, or 16-bit resolution
Dual 12-bit, 1 MSPS Output Digital-to-Analog Converter (DAC)
Two Analog Comparators (AC) with Window Compare function
One temperature sensor
Power-on Reset (POR) and Brown-out detection (BOD)
Internal and external clock options
External Interrupt Controller (EIC)
36 programmable I/O pins
1.71V – 3.6V
48-pin QFN