ATSAM4N8BA-AUR Microchip 32bit MCU

ATSAM4N8BA-AUR Overview

Microchip'sATSAM4N8B ARM® Cortex®-M4-based microcontroller runs at 100MHz and features 512KB of flash memory and 64KB of SRAM.

Peripherals include six USARTs, three SPIs and three I2Cs for fast serial communication, as well as a 10-channel 12-bit ADC, a 10-bit DAC, PWM, timers and RTC.

The device operates from 1.62V to 3.6 V and is available in 64-pin QFP and QFN packages.

Features

ARM Cortex-M4 running at up to 100 MHz
Memory Protection Unit (MPU)
DSP Instructions, Thumb®-2 instruction set
512 Kbytes embedded Flash
64 Kbytes embedded SRAM
8 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
Embedded voltage regulator for single-supply operation
Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for Safe Operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for RTT or system clock
Slow clock internal RC oscillator as permanent low-power mode device clock
High-precision 8/12 MHz factory-trimmed internal RC oscillator with 4 MHz default frequency for device startup, in-application trimming access for frequency adjustment
PLL up to 240 MHz for Device Clock
Temperature Sensor
Low-power tamper detection on two inputs, anti-tampering by immediate clear of general-purpose backup registers (GPBR)
23 Peripheral DMA Controllers
Sleep, Wait, and Backup modes, down to 0.7 μA in Backup mode with RTC, RTT, and GPBR
64-lead LQFP, 14 x 14 mm, pitch 0.5 mm
64-lead QFN, 9 x 9 mm, pitch 0.5 mm
Industrial (-40° C to +85° C)
2 USARTs with ISO7816, IrDA (only USART0), RS-485, and SPI Mode
4 two-wire UARTs
3 Two-wire Interfaces (TWI)
1 SPI
2 Three-channel 16-bit Timer Counter blocks with capture, waveform, compare and PWM mode, Quadrature Decoder Logic and 2-bit Gray Up/Down for Stepper Motor
1 Four-channel 16-bit PWM
32-bit low-power Real-time Timer (RTT) and low-power Real-time Clock (RTC) with calendar and alarm features
256-bit General Purpose Backup Registers (GPBR)
47 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination. Individually Programmable Open-drain, Pull-up and Pull-down resistor and Synchronous Output
Three 32-bit Parallel Input/Output Controllers, Peripheral DMA-assisted Parallel Capture mode
One 10-bit ADC up to 510 ksps, with Digital Averaging Function providing Enhanced Resolution Mode up to 12-bit, up to 16-channels
One 10-bit DAC up to 1 msps Internal voltage reference, 3V typ
Serial Wire/JTAG Debug Port(SWJ-DP)
Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access.
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
IEEE1149.1 JTAG Boundary-scan on all digital pins.
ASF-Atmel software Framework – SAM software development framework
Integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers.
DMA support, Interrupt handlers Driver support
USB, TCP/IP, Wi-Fi and Bluetooth, Numerous USB classes, DHCP and Wi-Fi encryption Stacks
RTOS integration, FreeRTOS is a core component