ATSAM3N0CA-CU Microchip 32bit MCU

ATSAM3N0CA-CU Overview

ARM® Cortex®-M3 SAM3N Microcontroller IC 32-Bit Single-Core 48MHz 32KB (32K x 8) FLASH 100-TFBGA (9x9)

Features

ARM Cortex-M3 revision 2.0 running at up to 48 MHz
Memory Protection Unit (MPU)
24-bit SysTick Counter
Nested Vector Interrupt Controller
DSP Instructions, Thumb®-2 instruction set
32 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane
8 Kbytes embedded SRAM
16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
Embedded voltage regulator for single-supply operation
Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for Safe Operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for RTT or system clock
Slow clock internal RC oscillator as permanent low-power mode device clock
High-precision 8/12 MHz factory-trimmed internal RC oscillator with 4 MHz default frequency for device startup, in-application trimming access for frequency adjustment
One PLL up to 130 MHz for device clock
Up to 10 Peripheral DMA (PDC) channels
Sleep, Wait, and Backup modes, down to 1.2 μA in Backup mode with RTC, RTT, and 256-bit GPBR
100-lead LQFP, 14 x 14 mm, pitch 0.5 mm
100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
Industrial (-40° C to +85° C)
2 USARTs with RS-485 and SPI mode support. One USART (USART0) has ISO7816, IrDA® and PDC support in addition
Two 2-wire UARTs
Two 2-wire Interfaces (I2C compatible)
One SPI
Two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode, Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
4-channel 16-bit PWM
32-bit low-power Real-time Timer (RTT)
Low-power Real-time Clock (RTC) with calendar and alarm features
79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination
Three 32-bit Parallel Input/Output Controllers
16 channels, 384 ksps 10-bit ADC
One 500 ksps 10-bit DAC
Serial Wire/JTAG Debug Port(SWJ-DP)
Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access.
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
IEEE1149.1 JTAG Boundary-scan on all digital pins.
ASF-Atmel software Framework – SAM software development framework
Integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers.
DMA support, Interrupt handlers Driver support
USB, TCP/IP, Wi-Fi and Bluetooth, Numerous USB classes, DHCP and Wi-Fi encryption Stacks
RTOS integration, FreeRTOS is a core component