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ADSP-2106x SHARC DSP Microcomputer Family
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The ADSP-21061 SHARCSuper Harvard Architecture Computeris a signal processing microcomputer that offers new capabilities and levels of performance. The ADSP-21061 SHARC is a 32-bit processor optimized for high performance DSP applications. The ADSP-21061 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dualported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.
KEY PROCESSOR CORE 50 MIPS, 20 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Dual data address generators with modulo and bit-reverse addressing Efficient program sequencing with zero-overhead looping: single-cycle loop setup IEEE JTAG Standard 1149.1 test access port and on-chip emulation 32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format 240-lead MQFP package, thermally enhanced MQFP, 225-ball plastic ball grid array (PBGA) Lead (Pb) free packages. For more information, see Ordering Guide on Page 52.
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