ADSP-21161NYCAZ110 Analog Devices 32bit DSP

ADSP-21161NYCAZ110 Overview

The ADSP-21161 SHARC® DSP is the newest member of the Super Harvard Architecture (SHARC) family of programmable DSPs. Capable of 600 million math operations per second (MFLOPs), the ADSP-21161 sets a new level of performance for low-cost SHARC DSPs - more than three times the performance for comparable models at about the same price. Its road map includes a cost-effective path to 1200 MFLOPS for $5 per unit and a performance-driven path to 10 GFLOPS and beyond.

"This newest edition to the SHARC family will open more possibilities for designers to design-in high performance digital signal processing into client-side applications and should help others reconsider applications they couldn’t do before with a single chip," said Will Strauss, president of Forward Concepts. "Analog Devices will certainly maintain customer loyalty with this road map."

The ADSP-21161 DSP is the second member of the SHARC DSP family of 32-bit floating-point programmable DSPs to be based on a SIMD core architecture that is optimized for digital signal processing performance. Like all SHARCs, the ADSP-21161 is code-compatible with all other members of the family and supports both fixed- and floating-point data types. The ADSP-21161 lowers the price for SIMD SHARC DSP performance and is an outstanding DSP solution for many price-sensitive applications.

State-of-the-Art Development Tools

The ADSP-21161, like all SHARC processors, is supported by a complete set of software and hardware development tools. The VisualDSP++® tool set offered by Analog Devices includes an optimizing C/C++ compiler, integrated development environment (IDE), assembler, linker, splitter and cycle accurate simulator that support both C and assembly debugging. Emulation support is JTAG-based and ADI offers USB, PCI, and Ethernet based emulators.

SHARC DSP Roadmap

There are two code-compatible paths that the SHARC DSP roadmap will follow. One optimized for high-performance multiprocessing systems and the other for price/performance. Performance is the key for multiprocessing applications and this is the reason that ADI will offer 10 GFLOP SHARC DSPs in the future. On-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 Mbit) using newly developed technologies.

Industry leading price/performance will be the driver on the other path of the roadmap. In the future, these SHARC DSPs will offer an increase in performance to 1200 MFLOPs while decreasing price to as low as $5.00. This is required to support new technologies that demand substantial signal processing performance at consumer price points.

ECAD Model

Footprint

Features

100 MHz (10 ns) SIMD SHARC DSP core
600 MFLOPS (32-bit floating-point data), 600 MOPS (32-bit fixed-point data)
Code-compatible with all SHARC DSPs
Supports IEEE-compatible 32-bit floating-point, 40-bit floating-point and 32-bit fixed-point math
Single-cycle instruction execution, including SIMD operations in both computational units
One Mbit on-chip dual-ported SRAM
2.4 Gbyte/sec on-chip data bandwidth

14 zero-overhead DMA channels
Four synchronous serial ports with I2S support
Serial ports support 128 channels TDM frames with selection of companding on a per channel basis
Integrated support for SDRAM and SBSRAM external memories
Support for single-cycle, 100 MHz instruction execution from x48-bit wide external memories