ADSP-21160NCBZ-100 Analog Devices 32bit DSP

ADSP-21160NCBZ-100 Overview

The ADSP-21160N SHARC® DSP is the second iteration of the ADSP-21160. Built in a 0.18 micron CMOS process, it offers higher performance and lower power consumption than its predecessor, the ADSP-21160M. Easing portability, the ADSP-21160N is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. To take advantage of the processor’s SIMD (Single Instruction, Multiple Data) capability, some code changes are needed. Like other SHARCs, the ADSP-21160N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160N includes a 100 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.

The ADSP-21160N introduces Single-Instruction, Multiple-Data (SIMD) processing. Using two computational units (ADSP-2106x SHARC DSPs have one), the ADSP-21160N can double performance versus the ADSP-2106x on a range of DSP algorithms.

The ADSP-21160N continues SHARC’s industry-leading standards of integration for DSPs, combining a high-performance 32-bit DSP core with integrated, on-chip system features. These features include a 4M-bit dual ported SRAM memory, host processor interface, I/O processor that supports 14 DMA channels, two serial ports, six link ports, external parallel bus, and glueless multiprocessing.

Features

100 MHz (10.5 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units
570 MFLOPS Peak and
380 MFLOPS Sustained Performance (Based on FIR)
Dual Data Address Generators (DAGs) with Modulo and Bit-Reverse Addressing
EEE 1149.1 JTAG Standard Test Access Port and On-Chip Emulation

Zero-Overhead Looping and Single-Cycle Loop Setup, Providing Efficient Program Sequencing
400-Ball 27 x 27 mm Metric PBGA Package
Single Instruction Multiple Data (SIMD) Architecture provides two computational processing elements, concurrent execution and code compatibility at assembly level with the ADSP-2106x SHARC DSP family