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ADSP-21061KSZ-200

ADSP-21061KSZ-200

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ADSP-21061KSZ-200 Overview

The ADSP-21061 is a member of the powerful SHARC ® familyof floating point processors. The SHARC ® ­Super HarvardArchitecture Computer­are signal processing microcomputersthat offer new capabilities and levels of integration and performance.

The ADSP-21061 is a 32-bit processor optimized forhigh performance DSP applications. The ADSP-21061 combinesthe ADSP-21000 DSP core with a dual-ported on-chipSRAM and an I/O processor with a dedicated I/O bus to form acomplete system-in-a-chip.

Fabricated in a high-speed, low-power CMOS process, theADSP-21061 has a 20 ns instruction cycle time operating at 50MIPS. With its on-chip instruction cache, the processor can executeevery instruction in a single cycle.

The ADSP-21061 SHARC ® combines a high-performancefloating-point DSP core with integrated, on-chip system features,including a 1 Mbit SRAM memory, host processor interface,DMA controller, serial ports and parallel bus connectivityfor glueless DSP multiprocessing.

ECAD Model

Footprint

ADSP-21061KSZ-200

Features

  • 50MHz (20ns instruction rate) SISD SHARC Core
  • 150MFLOPs peak performance
  • Code compatible with all SHARC processors
  • Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math
  • 1Mbit of on-chip dual-ported SRAM
  • Glueless connection for scalable DSP multiprocessing
  • Two synchronous serial ports with independent transmit and receive functions
  • 6 Channel DMA controller
  • Host Processor Interface

Applications

SHARC?

Specifications

  • Clock Rate 50MHz

  • Operating Temperature 0℃ ~ 85℃ (TC)

  • Type Floating Point

  • Non-Volatile Memory External

  • Package / Case 240-BFQFP Exposed Pad

  • Voltage - Core 5.00V

  • Voltage - I/O 5.00V

  • Mounting Type Surface Mount

  • Interface Synchronous Serial Port (SSP)

  • Supplier Device Package 240-MQFP-EP (32x32)

  • On-Chip RAM 128kB

Circuit Diagram

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