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DPLL (Digital Phase-Locked Loop) based network synchronizers, which generate and distribute clean output clocks to various sub-systems based on received network clocks, are critical components incommunication network equipment. The simplified diagram in Figure 1 demonstrates how network synchronizers are used in timing cards and line cards of typical communication equipment such as routers and switchers. To comply with requirements of communication standards such as ITU-T G.8262, network synchronizers are used to detect valid input clocks, filter input clock wander, and perform hitless switching and holdover functions. Low noise clocks are generated based on APLL's (Analog Phase-Locked Loop) locked to an external crystal reference oscillator (XO), or a temperature-compensated XO (TCXO) or an oven-stabilized XO (OCXO).
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