Introduction to the Zynq-7000 Gigabit Ethernet Controller

1 Introduction to the GEM

The Gigabit Ethernet Controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC compatible with the IEEE 802.3-2008 standard, capable of operating in half or full duplex mode at all three speeds.

The PS is equipped with two Gigabit Ethernet controllers, each of which can be configured independently. To access the pins through the MIO, each controller uses an RGMII interface (to save the pins) and accesses the PL through the EMIO that provides the GMII interface.

Additional Ethernet communication interfaces can be created in the PL using the GMII available on the EMIO interface, for example, the PL can be used to implement these interfaces.

•     SGMII and 1000 Base-X, in devices with GTX
•     RGMII v2.0 for PHY devices with HSTL Class 1 drivers and receivers

Registers are used to configure MAC features, select different modes of operation, and enable and monitor network management statistics. The DMA controller is connected to memory via the AHB bus interface, which connects to the FIFO interface of the MAC's controller, providing a decentralized-aggregation type of function for packet data storage in embedded processing systems.

The controller provides an MDIO interface for PHY management. Either MDIO interface of the PHY can be controlled from the following locations.

2 Block Diagram

The block diagram of an Ethernet controller is shown in the figure

Ethernet Controller

3 Features

Each Gigabit Ethernet MAC controller has the following features.

•    IEEE Standard 802.3-2008 compliant, supporting 10/100/1000 Mb/s transfer rates
•     Full and half duplex operation
•     RGMII interface to external PHYs when using the MIO pins
•     GMII/MII interface to PL allows soft-core connections to interfaces such as TBI, SGMII, 1000 Base-X and RGMII v2.0 support (note: SGMII and 1000 Base-X interfaces require Gigabit transceivers, MGT)
•     MDIO interface for physical layer management
•     32-bit AHB DMA master, 32-bit APB bus for control register access
•     Decentralized aggregation DMA function
•     Interrupt generation to signal reception and transmission completion, or error and wake-up
•     Automatic generation of padding and cyclic redundancy checks (CRC) on transmitted frames
•     Automatic discarding of received error frames
•     Programmable IPG stretching
•     Full duplex flow control with recognition of incoming pause frames and hardware-generated transmitted pause frames
•     Address checking logic for four specific 48-bit addresses, four type ID values, promiscuous mode, hash matching of unicast and multicast destination addresses, and LAN wake-up
•     802.1Q VLAN tagging to identify incoming VLANs and priority-tagged frames
•     Ethernet loopback mode support
•     IPv4 and IPv6 transport and receive IP, TCP and UDP checksum offload
•     Recognizes 1588 rev, 2 PTP frames
•     Statistics counter register for RMON/MIB

4 System Attempts

The following figure shows the Zynq system view of the Gigabit Ethernet controller.

5 Clock Domain

The Gigabit Ethernet controller has the following clocks.

•     AHB clock: The AHB clock used by the DMA block
•     APB clock: APB clock used by the MAC register block
•     TSU clock: Alternate clock source for the timestamp unit
•     TX clock: MAC transmit clock used by the MAC transmit module in MII/RGMII/GMII mode
•     Rx clock: MAC receive clock used in MII/RGMII/GMII mode MAC receive synchronization
•     Inverted TX clock: Inverted Tx clock for loopback mode