There is a lot of buzz about a new interface standard called JESD204B that addresses the digital interconnect between high-speed data converters and the digital processor. It uses a high-speed serial interface to transfer the digital data as opposed to the traditional, lower speed CMOS or LVDS interfaces. While this new interface promises many benefits, such as reduced overall design complexity, board space and cost savings, the system designer needs to carefully consider various design aspects when making the switch to the JESD204B interface. This paper examines the system implications around the JESD204B interface (Figure 1). Besides the sampling rate and AC performance specifications, there are several new parameters that influence the selection of the analog-to-digital (ADCs) or digital-to-analog converters (DACs).
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