STM32H743IIT6 STMicroelectronics ARM Microcontrollers MCU

STM32H743IIT6 Overview

STM32H742xI/G and STM32H743xI/G devices are based on the high-performance Arm® Cortex?-M7 32-bit RISC core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm? double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H742xI/G and STM32H743xI/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H742xI/G and STM32H743xI/G devices incorporate high-speed embedded memories with a dual-bank Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.

ECAD Model

Footprint

Features

32-bit Arm Cortex-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

Memories

Up to 2 Mbytes of Flash memory with read-while-write support
Up to 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), Up to 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
Dual mode Quad-SPI memory interface running up to 133 MHz
Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 100 MHz in Synchronous mode
CRC calculation unit

Security

ROP, PC-ROP, active tamper

General-purpose input/outputs

Up to 168 I/O ports with interrupt capability

Reset and power management

3 separate power domains which can be independently clock-gated or switched off:
- D1: high-performance capabilities
- D2: communication peripherals and timers
- D3: reset/clock control/power management
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
Voltage scaling in Run and Stop mode (6 configurable ranges)
Backup regulator (~0.9 V)
Voltage reference for analog peripheral/VREF+
Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging

Low-power consumption

VBAT battery operating mode with charging capability
CPU and domain power state monitoring pins
2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON)

Clock management

Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
External oscillators: 4-48 MHz HSE, 32.768 kHz LSE
3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode

Interconnect matrix

Specifications

Core Processor ARM Cortex M7
Speed 400MHz
Operating Temperature -40℃ ~ 85℃ (TA)
Program Memory Type FLASH
RAM Size 1M x 8
Number of I/O 140
Peripherals Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT
Mounting Type Surface Mount
Oscillator Type Internal
Supplier Device Package 176-LQFP (24x24)
Package / Case 176-LQFP
Core Size 32-Bit
Connectivity CANbus, EBI/EMI, Ethernet, I2C, IrDA, LINbus, MDIO, MMC/SD/SDIO, QSPI, SAI, SPDIF, SPI, SWPMI, UART/USART, USB OTG
Program Memory Size 2MB (2M x 8)
Data Converters A/D 20x16b; D/A 2x12b
Voltage - Supply (Vcc/Vdd) 1.62V ~ 3.6V