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SPC564L60L5CCFQR

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SPC564L60L5CCFQR Overview

The Leopard series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system.

The SPC56XL60/54 family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the SPC56XL60/54 automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users’ implementations.

Features

  • 1 MB flash memory with ECC
  • 128 KB on-chip SRAM with ECC
  • Built-in RWW capabilities for EEPROM emulation
  • SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection
    • Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch)
    • Fault collection and control unit (FCCU)
    • Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU
    • Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware
    • Boot-time Built-In Self-Test for ADC and flash memory triggered by software
    • Replicated safety enhanced watchdog
    • Replicated junction temperature sensor
    • Non-maskable interrupt (NMI)
    • 16-region memory protection unit (MPU)
    • Clock monitoring units (CMU)
    • Power management unit (PMU)
    • Cyclic redundancy check (CRC) unit
  • Decoupled Parallel mode for high-performance use of replicated cores
  • Nexus Class 3+ interface
  • Applications

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