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SPC560D30L1B4E0X

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SPC560D30L1B4E0X Overview

These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications.

This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology and designed specifically for embedded applications.
The advanced and cost-efficient e200z0h host processor core of this automotive controller family complies with the Power Architecture technology and only implements the VLE (variable-length encoding) APU (auxiliary processing unit) and provides improved code density. It operates at speed of up to 48 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with the user’s implementations.
The device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (SRAM) and internal flash memory.

ECAD Model

Symbol

SPC560D30L1B4E0X

Footprint

SPC560D30L1B4E0X

Features

  • 32-bit Power Architecture technology CPU
  • Variable length encoding (VLE)
  • Memory
    • Up to 256 KB Code Flash with ECC
    • Up to 64 (4x16) KB Data Flash with ECC
    • Up to 16 KB SRAM with ECC
  • Interrupts
    • 16 priority levels
    • Non-maskable interrupt (NMI)
    • Up to 38 external interrupts including 18 wakeup lines
  • 16-channel eDMA
  • GPIOs: 45 (LQFP64), 79 (LQFP100)
  • Timer units
    • 4-channel 32-bit periodic interrupt timers
    • 4-channel 32-bit system timer module
    • System watchdog timer
    • 32-bit real-time clock timer
  • 16-bit counter time-triggered I/Os
    • Up to 28 channels with PWM/MC/IC/OC
    • 5 independent counters
    • 27-channels with ADC trigger capability
  • 12-bit analog-to-digital converter (ADC) with up to 33 channels
    • Up to 61 channels via external multiplexing
    • Individual conversion registers
    • Cross triggering unit (CTU)
  • Applications

    Automotive, AEC-Q100, SPC56

    Specifications

    • Core Processor e200z0h

    • Speed 48MHz

    • Operating Temperature -40℃ ~ 105℃ (TA)

    • Program Memory Type FLASH

    • RAM Size 12K x 8

    • Number of I/O 45

    • Peripherals DMA, LVD, POR, PWM, WDT

    • Mounting Type Surface Mount

    • Oscillator Type Internal

    • Supplier Device Package 64-LQFP (10x10)

    • Package / Case 64-LQFP

    • Core Size 32-Bit

    • Connectivity CANbus, LINbus, SPI, UART/USART

    • Program Memory Size 128KB (128K x 8)

    • Data Converters A/D 16x12b

    • Voltage - Supply (Vcc/Vdd) 3V ~ 5.5V

    Circuit Diagram

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