RM48L952PGET

The RM48L952device is ahigh-performance microcontroller family forsafety systems. The safety architecture includesdual CPUs in lockstep, CPUand memory BIST logic, ECC on both the flash and the data SRAM, parityonperipheral memories, and loopback capability on peripheral I/Os.

The RM48L952deviceintegrates the ARM Cortex-R4FFloating-PointCPU. The CPU offers an efficient 1.66 DMIPS/MHz, and hasconfigurations thatcan run up to 220MHz, providing up to 365 DMIPS.The device supports thelittle-endian [LE]format.

The RM48L952 device has 3MB ofintegrated flash and 256KB of data RAM.Both the flash andRAM have single-bit error correction and double-bit errordetection. The flash memory on thisdevice is a nonvolatile, electricallyerasable, and programmable memory implemented with a64-bit-wide data businterface. The flash operates on a 3.3-V supply input (same level as I/Osupply) for all read, program, and erase operations. When in pipeline mode, theflash operates witha system clock frequency of up to 220 MHz.The SRAMsupports single-cycle read and write accesses in byte, halfword, word, anddouble-wordmodes.

The RM48L952devicefeatures peripherals for real-time control-basedapplications, including twoNext Generation High-End Timer (N2HET) timingcoprocessors and two 12-bit Analog-to-DigitalConverters (ADCs) supporting upto 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timingfunctionsfor real-time applications. The timer is software-controlled, usinga reduced instruction set, witha specialized timer micromachine and anattached I/O port. The N2HET can be used forpulse-width-modulated outputs,capture or compare inputs, or GPIO. The N2HET is especially wellsuited forapplications requiring multiple sensor information and drive actuators withcomplex andaccurate time pulses. A High-End Timer Transfer Unit (HTU) canperform DMA-type transactions totransfer N2HET data to or from main memory.A Memory Protection Unit (MPU) is built into theHTU.

Thedevice has two 12-bit-resolution MibADCs with 24 channels and 64 wordsof parity-protected bufferRAM each. The MibADC channels can be convertedindividually or can be grouped by software forsequential conversionsequences. Sixteen channels are shared between the two MibADCs. There arethree separate groupings. Each sequence can be converted once when triggered orconfigured forcontinuous conversion mode. The MibADC has a 10-bit mode foruse when compatibility with olderdevices or faster conversion time isdesired.

Thedevice has multiple communication interfaces: three MibSPIs,twoSPIs, one LIN, one SCI, three DCANs,one I2C module, oneEthernet, and oneUSB module. The SPIsprovide a convenient method of serial high-speedcommunication between similar shift-register typedevices. The LIN supportsthe Local Interconnect standard 2.0 and can be used as a UART infull-duplexmode using the standard Non-Return-to-Zero (NRZ) format.

TheDCAN supports the CAN 2.0 (A and B) protocol standard and uses aserial, multimaster communicationprotocol that efficiently supportsdistributed real-time control with robust communication rates ofup to 1Mbps. The DCAN is ideal for systems operating in noisy and harsh environments(for example,automotive vehicle networking and industrial fieldbus) thatrequire reliable serial communicationor multiplexed wiring.

The Ethernet module supports MII, RMII, and MDIO interfaces.

The USB module includes a 2-port USB host controller. Itis revision2.0-compatible, based on the OHCI specification for USB, release 1.0. The USBmodulealso includes a USB device controller compatible with the USBspecification revision 2.0 and USBspecification revision 1.1.

TheI2C module is a multimaster communication module providing aninterface between the microcontrollerand an I2C-compatible devicethrough the I2Cserial bus. The I2C supports speeds of100 and 400 Kbps.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used tomultiply theexternal frequency reference to a higher frequency for internaluse. There are two FMPLL modules onthis device. These modules, when enabled,provide two of the seven possible clock source inputs tothe Global ClockModule (GCM). The GCM manages the mapping between the available clock sourcesandthe device clock domains.

The device also has an External Clock Prescaler (ECP) module that whenenabled, outputsa continuous external clock on the ECLK pin (or ball). TheECLK frequency is a user-programmableratio of the peripheral interface clock(VCLK) frequency. This low-frequency output can bemonitored externally as anindicator of the device operating frequency.

The DMA controller has 16 channels, 32 peripheral requests, and parityprotection on its memory. An MPU is built into the DMA to limit the DMA toprescribed areas ofmemory and to protect the rest of the memory system fromany malfunction of the DMA.

The Error Signaling Module (ESM) monitors all device errors and determineswhether aninterrupt is generated or the external ERRORpin is toggled when a fault isdetected. The ERRORpin can be monitored externally as an indicator of afault condition in themicrocontroller.

TheExternal Memory Interface (EMIF) provides off-chip expansioncapability with the ability tointerface to synchronous DRAM (SDRAM) devices,asynchronous memories, peripherals, or FPGAdevices.

Severalinterfaces are implemented to enhance the debugging capabilitiesof application code. In additionto the built-in ARM Cortex-R4F CoreSightdebug features, an External Trace Macrocell (ETM) providesinstruction anddata trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM andperipheral accesses by the CPUor any other master. A Data ModificationModule (DMM) gives the ability to write external data intothe device memory.Both the RTP and DMM have no or only minimum impact on the program executiontime of the application code. A Parameter Overlay Module (POM) can reroute flashaccesses tointernal memory or to the EMIF. This rerouting allows the dynamiccalibration against productioncode of parameters and tables withoutrebuilding the code to explicitly access RAM or halting theprocessor toreprogram the data flash.

With integrated safety features and a wide choice of communication andcontrolperipherals, the RM48L952 device is anideal solution forhigh-performance real-time control applications with safety-critical