P5040NSN7TMC NXP SOC

P5040NSN7TMC Overview

The QorIQ® P5 family delivers scalable, 64-bit processing with single-, dual-, and quad-core devices. With frequencies scaling up to 2.2 GHz, a tightly coupled cache hierarchy for low latency, and integrated hardware acceleration, the P5040 (quad-core) and P5021 (dual-core) devices are ideally suited for compute-intensive, power-conscious control plane applications.

Features

Four (P5040) or two (P5021) single-threaded e5500 cores built on Power Architecture® technology
Up to 2.2 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
Three levels of instruction: user, supervisor, hypervisor
Hybrid 32-bit mode to support legacy software and transition to 64-bit architecture
2.0 MB configures as dual 1 MB platform cache

NETWORKING ELEMENTS

SerDes
- 20 lanes at up to 5 Gbps
- Supports SGMII, XAUI, PCI Express® (PCIe) rev1.1/2.0, SATA
Ethernet interfaces
- Two 10 Gbps Ethernet MACs
- Ten 1 Gbps Ethernet MACs

ACCELERATORS AND MEMORY CONTROL

Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support
- Up to 1600MT/s
DPAA incorporating acceleration for the following functions
- Packet parsing, classification, and distribution (FMAN)
- Queue management for scheduling, packet sequencing and congestion management (QMAN)
- Hardware buffer management for buffer allocation and de-allocation (BMAN)
- Cryptography acceleration (SEC 5.2) at up to 20Gbps
RAID 5 and 6 storage accelerator with support for end-to-end data protection information

BASIC PERIPHERALS AND INTERCONNECT

Three PCIe 2.0/3.0 controllers
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Four I²C controllers
Two DUARTs
Integrated flash controller supporting NAND and NOR flash
Two 4-channel DMA engines

ADDITIONAL FEATURES

Support for hardware virtualization and partitioning enforcement
- Extra privileged level for hypervisor support
QorIQ® trust architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage