MPC8265ACZUMIBC NXP MPU

MPC8265ACZUMIBC Overview

The PowerQUICC® II™ integrated communications processor family delivers excellent integration of processing power for networking and communications peripherals, providing customers with an innovative, total system solution for building high-end communications systems. NXP® Semiconductors's PowerQUICC II processor family is the next generation of the leading PowerQUICC™ line of integrated communications processors, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration.

Our leading PowerQUICC architecture integrates two processing blocks. One block is a high-performance embedded G2 core and the second block is the Communications Processor Module (CPM). The CPM of the PowerQUICC II processor can support up to three fast serial communications controllers (FCCs), two multichannel controllers (MCCs), four serial communications controllers (SCCs), two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I2C interface. The combination of the G2 core and the CPM, along with the versatility and performance of the PowerQUICC II processor family, provides customers with enormous potential in developing networking and communications products while significantly reducing time-to-market development stages.

Features

300 MHz high-speed embedded G2 core
Powerful memory controller and system functions
Enhanced 32-bit RISC communications processor module
Up to three multiport 10/100 Mbps ethernet MAC
Up to two UTOPIA ports (155 Mbps ATM)
Up to 256 HDLC channels (each channel 64 Kbps, full duplex)
Up to four 10 Mbps ethernet MAC
Transmission convergence sub-layer and inverse multiplexing for ATM capabilities
Integrated PCI interface
Strong 3rd-party tools support from 恩智浦合作伙伴计划 partner program members

Typical Applications

Remote Access Concentrators
Regional Office Routers
Cellular Infrastructure equipment
Telecom Switching Equipment
Ethernet Switches
T1/E1-to-T3/E3 Bridges
xDSL Systems

Technical Specifications

Embedded G2 core available from 133 - 300 MHz
- 190 MIPS at 100 MHz (Dhrystone 2.1)
- 505 MIPS at 266 MHz (Dhrystone 2.1)
- 570 MIPS at 300 MHz (Dhrystone 2.1)
- High-performance, superscalar microprocessor
- Disable CPU mode
- Supports the NXP® external L2 cache chip (MPC2605)
- Improved low-power core
- 16 Kbyte data and 16 Kbyte instruction cache
- Memory Management Unit
- Floating Point Unit
- Common On-chip Processor (COP)
System Interface Unit (SIU)
- Memory controller, including two dedicated SDRAM machines
- PCI up to 66 MHz
- Hardware bus monitor and software watchdog timer
- IEEE 1149.1 JTAG test access port
High-Performance CPM with operating frequency up to 133, 166, or 200 MHz
- G2 core and CPM may run at different frequencies
- Parallel I/0 registers
- On-board 32 KBytes of dual-port RAM
- Two multi-channel controllers (MCCs), each supporting 128 full-duplex, 64 Kbps, HDLC lines
- Virtual DMA functionality
- Three FCCs supporting:
- Up to 155 Mbps ATM SAR (maximum of two) (AAL0, AAL1, AAL2,AAL5)
- 10/100 Mbps Ethernet (up to three) (IEEE 802.3X with Flow Control)
- 45 Mbps HDLC / Transparent (up to three)
- Two UTOPIA Level II master/slave ports with multi-PHY support.
- Three MII interfaces
- Eight TDM interfaces (T1/E1), two TDM ports can be interfaced with T3/E3
- Transmission Convergence Layer capabilities
- Integrated Inverse Multiplexing for ATM (IMA) functionality
Two bus architectures: one 64-bit 60x bus and one 32-bit PCI or local bus
- Integrated PCI interface
1.8V or 2.0V internal and 3.3V I/O
300 MHz power consumption: 2.5 W
480 TBGA package (37.5 x 37.5 mm)
IMA/TC layer functionality
Integrated PCI capability