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18-Mbit QDR⑩-II SRAM 2 Word Burst Architecture,SRAM 1Mx18 1.8V DDR II SRAM
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The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.
• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C130/CY7C131 easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input on CY7C140/CY7C141
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC, 52-Pin TQFP.
• Pb-Free packages available
Mounting Style SMD/SMT
Maximum Operating Current 550 mA
Type Synchronous
Access Time 0.45 ns
Memory Size 18 Mbit
Package / Case FBGA
Maximum Clock Frequency 200 MHz
Maximum Operating Temperature + 70 C
Supply Voltage - Max 1.9 V
Supply Voltage - Min 1.7 V
Minimum Operating Temperature 0 C
Factory Pack Quantity 119
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