ADUCM4050BCBZ-R7 Analog Devices 32bit MCU

ADUCM4050BCBZ-R7 Overview

The ADuCM4050 microcontroller unit (MCU) is an ultra low power integrated microcontroller system with integrated power management for processing, control, and connectivity. The MCU system is based on the ARM® Cortex®-M4F processor. The MCU also has a collection of digital peripherals, embedded static random access memory (SRAM) and embedded flash memory, and an analog subsystem that provides clocking, reset, and power management capabilities in addition to an analog-to-digital converter (ADC) subsystem.

This data sheet describes the ARM Cortex-M4F core and memory architecture used on the ADuCM4050 MCU. It does not provide detailed programming information about the ARM processor.

The system features include an up to 52 MHz ARM Cortex-M4F processor, 512 kB of embedded flash memory with error correction code (ECC), an optional 4 kB cache for lower active power, and 128 kB system SRAM with parity. The ADuCM4050 features a power management unit (PMU), multilayer advanced microcontroller bus architecture (AMBA) bus matrix, central direct memory access (DMA) controller, and beeper interface.

The ADuCM4050 features cryptographic hardware supporting advanced encryption standard (AES)-128 and AES-256 with secure hash algorithm (SHA)-256 and the following modes: electronic code book (ECB), cipher block chaining (CBC), counter (CTR), and cipher block chaining-message authentication code (CCM/CCM*) modes.

The ADuCM4050 has protected key storage with key wrap/ unwrap, and keyed hashed message authentication code (HMAC) with key unwrap.

The ADuCM4050 supports serial port (SPORT), serial peripheral interface (SPI), I2C, and universal asynchronous receiver/ transmitter (UART) peripheral interfaces.

The ADuCM4050 features a real-time clock (RTC), general-purpose and watchdog timers, and programmable general-purpose input/output (GPIO) pins. There is a hardware cyclic redundancy check (CRC) calculator with programmable generator polynomial. The device also features a power on reset (POR) and power supply monitor (PSM), a 12-bit successive approximation register (SAR) ADC, a red/green/blue (RGB) timer for driving RGB LED, and a true random number generator (TRNG).

To support low dynamic and hibernate power management, the ADuCM4050 MCU provides a collection of power modes and features such as dynamic- and software-controlled clock gating and power gating.

For full details on the ADuCM4050 MCU, refer to the ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference.

Product Highlights

Ultra low power consumption.

Robust operation.

Full voltage monitoring in deep sleep modes.

ECC support on flash.

Parity error detection on SRAM memory.

Leading edge security.

Fast encryption provides read protection to user algorithms.

Write protection prevents device reprogramming by unauthorized code.

Failure detection of 32 kHz low frequency external crystal oscillator (LFXTAL) via interrupt.

SensorStrobe™ for precise time synchronized sampling of external sensors. Works in hibernate mode, resulting in drastic current reduction in system solutions. Current consumption reduces by 10 times when using, for example, the ADXL363 accelerometer. Software intervention is not required after setup. No pulse drift due to software execution.

Applications

Internet of Things (IoT)
Smart agriculture, smart building, smart metering, smart city, smart machine, and sensor network
Wearables
Fitness and clinical
Machine learning and neural networks

Features

EEMBC ULPMark™-CP score (3 V): 189
Ultra low power active and hibernate modes
Active mode dynamic current: 41 μA/MHz (typical)
Flexi mode: 400 μA (typical)
Hibernate mode: 0.65 μA (typical)
Shutdown mode: 50 nA (typical)
Shutdown mode (fast wake-up): 0.20 μA (typical)
ARM Cortex-M4F processor at 52 MHz with FPU, MPU, ITM with SWD interface
Power management
Single-supply operation (connected to VBAT pins): 1.74 V to 3.6 V
Optional buck converter for improved efficiency
Memory options
512 kB of embedded flash memory with ECC
4 kB of cache memory to reduce active power
128 kB of configurable system SRAM with parity
Safety
- Watchdog with dedicated on-chip oscillator
- Hardware CRC with programmable polynomial
- Multiparity bit protected SRAM
- ECC protected embedded flash
Security
- Hardware cryptographic accelerator supporting AES-128, AES-256, and SHA-256
- Protected key storage in flash, SHA-256-based keyed
- HMAC and key wrap and unwrap
- User code protection
- TRNG

Digital peripherals
- 3 SPI interfaces to enable glueless interface to sensors, radios, and converters
- 1 I2C and 2 UART peripheral interfaces
- SPORT for natively interfacing with converters and radios
  - Programmable GPIOs (44 in LFCSP and 51 in WLCSP)
- 3 general-purpose timers with PWM support
- RGB timer for driving RGB LED
- RTC0 for time keeping
- RTC1 with SensorStrobe and time stamping
- Programmable beeper
- 27-channel DMA controller
Clocking features
- 26 MHz clock: on-chip oscillator, external crystal oscillator, SYS_CLKIN for external clock, and integrated PLL
- 32 kHz clock: on-chip oscillator and low power crystal oscillator
- Clock fail detection for external crystals
Analog peripherals
- 12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital comparator