ADSP-21469BBCZ-3 Analog Devices DSP

ADSP-21469BBCZ-3 Overview

The fourth generation of SHARC® Processors, which includes theADSP-21469, offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.

The ADSP-21469 offers the highest performance – 450 MHz/2700 MFLOPs -- within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21469 particularly well suited to address the increasing requirements of the professional and automotive audio market segments. In addition to its higher core performance, the ADSP-21469 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to faster external memory by providing a glueless interface to 16-bit wide DDR2 SDRAMs.

Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller.Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

Features

450 MHz core clock speed
5 Mbits of on-chip RAM
FIR, IIR, and FFT accelerators
16-bit wide DDR2 external memory interface
Digital Applications Interface (DAI) enabling user-definable access to peripherals including an S/P DIF Tx/Rx, and 8-channel asynchronous sample rate converter
Fully enhanced DMA engine including scatter/gather DMA, delay line DMA
2 Link Ports

8 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes
2 SPI-compatible ports supporting master and slave modes
UART and Two-Wire Interface
16 Pulse Width Modulation (PWM) channels
3 full-featured timers
324-ball CSP_BGA package
Commercial and Industrial temperature ranges